A stacked-capacitor DRAM cell comprises an MOS transistor and a storage capacitor, the MOS transistor being disposed in a silicon substrate and the storage capacitor comprising two doped polysilicon layers and a dielectric layer disposed inbetween, said layers being disposed at the surface of the substrate. In this arrangement the storage capacitor completely or partly spans that area which is covered by the transistor.
In order to increase the capacitance of the storage capacitor further for the same size of the area covered on the substrate and, consequently, to reduce the area required on the substrate for constant capacitance of the storage capacitor, it has been proposed to construct the storage capacitor cylindrically. For this purpose, the storage node, i.e. that electrode of the storage capacitor on which the information is stored in the form of charge, is cylindrically constructed. In addition to the base area, which is disposed at the surface of the substrate, it comprises an upwardly projecting lateral area. The dielectric layer is disposed on the surface of the base area and on the inside and outside of the surface of the lateral area. The cell plate, i.e. the second electrode of the storage capacitor, is then disposed on the surface of the dielectric layer. In this way, the area of the capacitor can be radically increased compared with the area required on the substrate.
To produce the storage capacitor, an auxiliary layer is first prepared on the surface of the substrate. Openings are made in said auxiliary layer. To form the storage nodes, a thin layer of doped polysilicon is deposited on the auxiliary layer having the openings. That part of the polysilicon layer deposited on the side walls and the base of the openings forms the subsequent storage nodes. The side walls of the openings should therefore be as vertical as possible.
After forming the storage nodes by removing the component of the polysilicon layer on the surface of the auxiliary layer and after removing the auxiliary layer, a storage dielectric is deposited over the entire surface. This extends both on the inside areas and on the outside areas of the free-standing lateral part of the storage node. The cell plate is then deposited over the entire surface as counterelectrode.
The auxiliary layer is deposited on the surface of the substrate, in which surface the MOS transistors have previously been produced. Between the storage nodes and the respective active regions of the associated transistors, a cell contact has to be made. This may follow directly or via additional, electrically conducting structures. Before the deposition of the auxiliary layer, the surface of the substrate is, as a rule, covered with an insulating layer. During the production of the opening in the auxiliary layer, it is necessary to ensure that an uncontrolled structuring of the insulating layer situated underneath the auxiliary layer does not occur. If, in addition to the cell contacts, holes extending to still other conductive regions are produced in the insulating layer during the production of the openings, these result in short circuits to the storage nodes subsequently formed. This should be avoided.
To solve this problem, it is known from W. Wakamiya et al., Symp. on VLSI Technology 1989, p.69, to form a polysilicon underlayer, in the region of the storage nodes, under the auxiliary layer which is formed from SiO.sub.2. This underlayer is produced before depositing the auxiliary layer by depositing a polysilicon layer over the entire surface and then structuring using a photoresist mask. The size of the polysilicon underlayer is dimensioned in such a way that the SiO.sub.2 etching to form the opening in the auxiliary layer certainly encounters it. The polysilicon underlayer acts as an etch stop in this etching process. The polysilicon underlayer remains in the storage cell as part of the subsequent storage node.
From Y. Kawamoto et al., Symp. on VLSI Technology 1990, p.13, it is known to form the auxiliary layer from polyimide. The production of the openings in the auxiliary layer is then not critical since polyimide can be etched with good selectivity with respect to SiO.sub.2. To produce the storage nodes, a polysilicon layer is deposited on the surface of the polyimide auxiliary layer after producing suitable openings. Because of the low thermal stability of the polyimide, the temperature has to be limited during the polysilicon deposition.
From T. Kaga et al., IEEE Trans. Electr. Dev., vol.38, 1991, p.255, it is known to use a composite layer of Si.sub.3 N.sub.4 and SiO.sub.2 as auxiliary layer. The openings are formed in the SiO.sub.2 and in the Si.sub.3 N.sub.4. A special plasma etching process which etches with a selectivity of 40:1 relative to SiO.sub.2 is necessary to form the opening in the Si.sub.3 N.sub.4.